1. Field of the Invention
The present invention relates to a method of manufacturing a wafer level package; and, more particularly, to a method of manufacturing a wafer level package to coat resin on a dicing line formed on a substrate wafer.
2. Description of the Related Art
A conventional package is manufactured by cutting a wafer having a plurality of chips along dicing lines to be divided into individual chips and then performing a packaging process for each of the individual chips.
However, because the packaging process includes a lot of unit processes, e.g., chip attaching, wire bonding, molding, trimming/forming or the like, a conventional method of manufacturing the package to perform the packaging process by each of the chips has a disadvantage of needing a very long time for packaging all of the chips when considering the number of the chips obtained from one wafer.
Therefore, recently, there has been suggested a wafer level package method of manufacturing an individual package by firstly performing the packaging process in a wafer level and then cutting a wafer level package along dicing lines of a wafer.
In the wafer level package, it is general that after a molding process is performed on the wafer provided with a chip or the like by using molding resin such as EMC(Epoxy Mold Compound), the surface of the molding resin is formed to be flat. However, if the molding resin has the flat surface, the CTE(Coefficient of Thermal Expansion) of the molding resin is more than double to ten times the CTE of the wafer and so the molding resin may be considerably contracted due to heat generated in the molding process, which causes a warpage phenomenon where the wafer is rolled and makes the dicing lines unseen.